Default bin Usage

SystemVerilog
,
1

I have 2 codes below ::


coverpoint tr.kind  //  4- bit variable
{
  bins  zero = { 0 } ;
  bins  lo   =  { [1:3] } ;
  bins  hi[]  =  { [8:$] } ;
  bins  misc  =  default ;
}



//  Without  default  bin
coverpoint tr.kind  //  4- bit variable
{
  bins  zero = { 0 } ;
  bins  lo   =  { [1:3] } ;
  bins  hi[]  =  { [8:$] } ;
}

**Since default bins do not contribute to coverage , what are the benefits of defining them ?

Without them coverage would still be calculated based on the number of user-defined bins right ?**

2

In reply to hisingh:

For debugging.

3

In reply to dave_59:

Hi Dave ,
By debugging do you mean that coverage report would show when default bins are covered / hit ?
( although they aren’t used for coverage calculation)

4

In reply to hisingh:

Yes, just to show that your sampling is working, just not seeing your expected data.