Declaring class handle as rand

SystemVerilog
, ,
1

What happens when we declare class handle as rand type?
will it affects the randomization??
I am trying to do sorting using constraint guards.

Thanks in Advance!!

2

In reply to Anil Sharma:

as per my understanding
without rand before a class handle, if it is used in other class , randomization wont work

If you declare rand qualifier before a class and use this handle inside some other class , randomization works properly

try removing rand qualifier before and run simulation ,
like below
rand packet pkt1 —> working
packet pkt1 —> not working

Also you can refer another link in this forum

3

if you will ramdomize the handle name of the class .

example: class fldec;
bit[31:0] A;
bit B;
bit C;
bit shubham;
function fun();

endfunction

initial
begin
fldec fl;
end
initial
begin
fl.randomize();
end
endclass

than you all the properties(variables inside the class) will get randomize.

4

thanks for the explanation.

But I am trying the code mention in the LRM,
please help me to rectify the null pointer error in the code.

5

In reply to hurmath@fldec:

if you will ramdomize the handle name of the class .
example: class fldec;
bit[31:0] A;
bit B;
bit C;
bit shubham;
function fun();
endfunction
initial
begin
fldec fl;
end
initial
begin
fl.randomize();
end
endclass
than you all the properties(variables inside the class) will get randomize.

I got you, but my question is different than what you had explained. Please refer to the previous reply of mine. I have mentioned the eda link help me with that. You can find the same code in the LRM under constraint guards section.
Thanks.

6

In reply to Anil Sharma:

I think you are dealing with a tool issue, try a different one.

7

In reply to dave_59:

In reply to Anil Sharma:
I think you are dealing with a tool issue, try a different one.

Thanks dave,
Initially, I was trying with Synopsys VCS 2014.10 and I got a warning like this
Warning-[CNST-PPRW] Constraint randomize NULL object warning

Then I tried with cadence incisive 15.20
My outputs came like this → 14 2 9 2 19 11 9 14 14 8

which is not in ascending fashion.

I got the same with the Aldec Riviera Pro 2015.02 I got the output like cadence but here as well it was not in ascending order…

Should I go for the higher version of VCS?

code link Constraint Guards - EDA Playground

8

In reply to Anil Sharma:

You only construct one class a object and repeatedly randomize the same object.