Declaration and placement inside a function

SystemVerilog
1

Hi,
I wonder why I get a wrong value when I try to declare and place a value at the same time inside a function.

//aaton[1] = 2000
//aaton[0] = 1000
 
  function is_dni_type check_is_dni (input realtime aaton[int], aatoff[int]);
    realtime first_ton; = aaton[1] - aaton[0];
    realtime first_toff; = aatoff[1] - aatoff[0];
      
    first_ton = aaton[1] - aaton[0];
    first_toff; = aatoff[1] - aatoff[0];
    $display("first ton is:=%0t",aaton[1] - aaton[0]); //the value is: 1000
    $display("first ton is:=%0t",first_ton); //the value is: 0
    
   // return is_dni_type'(1);
  endfunction : is_dni

Thanks,
Tomer

2

In reply to tomermarguy:

If this function is not a class method, see function arguments not initializing variable inside the body | Verification Academy