Hello, I’m working on a parser for extracting the implicitly inferred data type and signedness from a constant expression assigned to a parameter. Although in the LRM it is stated that:
“Simple decimal numbers without the size and the base format shall be treated as signed integers, whereas the
numbers specified with the base format shall be treated as signed integers”
I can see that, using $display in an online Verilog simulator which I assume would behave similarly to SystemVerilog on this concept, if the size declared in the base format isn’t 32 bits then the binary representation isn’t casted to an integer since it doesn’t have 32 bits as a simple decimal does.