Data type of a number specified with a base format

Hello, I’m working on a parser for extracting the implicitly inferred data type and signedness from a constant expression assigned to a parameter. Although in the LRM it is stated that:

“Simple decimal numbers without the size and the base format shall be treated as signed integers, whereas the
numbers specified with the base format shall be treated as signed integers”

I can see that, using $display in an online Verilog simulator which I assume would behave similarly to SystemVerilog on this concept, if the size declared in the base format isn’t 32 bits then the binary representation isn’t casted to an integer since it doesn’t have 32 bits as a simple decimal does.

In reply to vasilissoti:

This was recently clarified in the next revision on the IEEE 1800 SystemVerilog LRM.

An integer literal constant is a vector (see 7.4) of type logic with range [n-1:0], where n is the number of bits in the constant, as specified above. The vector is signed if the constant is signed, and unsigned otherwise.

And in another clarification it mentions that an unsized literal is at least 32-bits or the minimum size to represent the value.