Cyclic randomization of a large variable

SystemVerilog
1

I have a 33 bit “rand” addr and I don’t want the addresses to be repeated for the same test run. I changed the variable to be randc, but got this error during VCS compilation.

Error-[RCNAOLV] Randc not allowed on large variables

How can I get around this issue, yet avoid repetition of addresses for a simulation run? I cannot reduce the size of addr to be <32 bits.

Thanks

2

In reply to UVM_learner6:

https://verificationacademy.com/forums/systemverilog/how-can-we-generate-randc-behaviour-rand-variable#reply-41226