Cyclic randomization behavior without 'randc' keyword

SystemVerilog
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1

Can anyone give an idea on how to bring cyclic randomization without using randc keyword and queue/array as for reference

Common methods for genearting cyclic randomization is

  1. Using randc keyword
  2. using a queue/array, checking whether element to be randomized has values in queue/array and pushing the newely randomized value into the array in post_randomize()

I am trying to get the cyclic randomization behavior with methods not mentioned above

2

In reply to bachan21:

3

In reply to bachan21:

class abc;
  rand logic[2:0] a;
  int saved[$];
  
  constraint c1 { !(a inside saved);}
  
  function void post_randomize();
    saved.push_back(a);
    if(saved.size == 2**3)begin
      saved = {};
    end 
  endfunction
  
endclass

module abc;
  abc a1;
  
  initial begin
    a1 = new();
    repeat(8)begin
    a1.randomize();
    $display(a1.a);
    end
  end 
endmodule
4

In reply to yourcheers:

I am trying to implement my intention without post_randomize or unique keyword.
Any further thoughts?

P.S. Kudos to your clean coding. Thumbs up

5

In reply to bachan21:

[1] Try the same logic in pre_randomize()

[2] Have a Simple Counter which increments in pre_randomize()

6

In reply to bachan21:

There is absolutely no way of replicaiting the functionality of the randc modifier without using an array of used or unused values. If there are any constraints on the random variable, you have no idea how many values need to be generated before you need to restart the cycle.

If you are looking for a synthesizable cycle of noncontiguous values, you might want to study linear feedback shift registers (LFSRs).

It might help to explain where your requirements are coming from if not just an interview question.

7

In reply to dave_59:

Thanks Dave
I wanted to see if there is any possibility for this problem than the conventional methods for cyclic randomization