Coverpoint bin set_covergroup_expression is unclear

SystemVerilog
,
1

it’s unclear to me how “set_covergrup_expression” is used, it’s defined in IEEE 1800-2012,
can any one give an example about this point ?!

2

I have an example here: Get Ready for SystemVerilog 2012 - Verification Horizons

3

In reply to dave_59:

Is the blog is not accessible anymore ? I get below error
blogs.mentor.com’s server IP address could not be found.

4

In reply to Navdeep Kaur:

Sorry, a few kinks in the transition to Siemens EDA. I’ve updated the link.