Coverage for parameterized varaiable

SystemVerilog
,
1

Hi

I am trying to write coverage for a signal which has variable width.

bit [PARAM_MSB-1:0] signal_a;

I want to write a coverpoint where i want only the bins which have 1 in each bit location.

For example: If PARAM_MSB is 3, I want the bins of signal_a to be created only for values of {1,2,4} and {0,3,5,6,7} have to be ignored.
As PARAM_MSB value is varaiable, I cannot have these bins hard-coded.

Please provide a way to write this coverage.

2

In reply to venkateshkadimi:

Are you just interested in bin values that are a power of two? Then it doesn’t matter what value PARAM_MSB is and you can write a covergroup like so.


covergroup cvrgrp;
    coverpoint signal_a
    {
        bins power_of_two[] = signal_a with ($countones(item) == 1);
        bins not_power_of_two = default;
    }
endgroup

If your bin values are arbitrary, then you can make multiple covergroups based on PARAM_MSB.


case (PARAM_MSB)
    3: begin
       // Covergroup for PARAM_MSB = 3
    end

    4: begin
       // Covergroup for PARAM_MSB = 4
    end
endcase