Coverage Conditions

SystemVerilog
1

Hi,

I have

 bit [7:0] a;
 bit [3:0] b;

I want to have bins for concatenation of {a,b} such that every bit of b is set to 1 and every two bits of a to have atleast a 1 like

b = {4'b0001},{4'b0100}, {4'b0010}, {4'b1000}
 a is like a[7:6] should have atleast one bit set
           a[5:4] should have atleast one bit set
           a[3:2] should have atleast one bit set
           a[1:0] should have atleast one bit set

so total of 8 bins. And also when a is hitting b should be always 0 and viceversa . Please help me out

Thanks
AnudeepJ

2

The mentioned problem can be solved using two coverpoints.

covergroup cg;

   cp_a : coverpoint a iff ( b == 0) {
       bins a_7_6 = { [ 2**6 : 2**7 + 2**6 ] };
       bins a_5_4 = { [ 2**4 : 2**5 + 2**4 ] };
       bins a_3_2 = { [ 2**2 : 2**3 + 2**2 ] };
       bins a_1_0 = { [ 2**0 : 2**1 + 2**0 ] };
   }

   cp_b : coverpoint b iff ( a == 0) {
       bins b_0 = { 2**0 };
       bins b_1 = { 2**1 };
       bins b_2 = { 2**2 };
       bins b_3 = { 2**3 };
   }

endgroup : cg