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  • Coverage for an assertion.

Coverage for an assertion.

SystemVerilog 6730
#systemverilog 610 #SystemVerilog ... 19
sarth21
sarth21
Full Access
22 posts
January 03, 2019 at 11:18 pm

Hello I am writing some immediate assertions. The assertion is like when the enable is active a counter should be maintained.
I came up with the understanding that counter should exist with some value so the assertion:

assert final (enable & cnt_en & cnt >= 'd0)
 else
   $display("assertion failed");
 
cover final (enable & cnt_en & cnt >= 'd0)
   $info(" assertion covered");

I am getting pass for this one ,however my question is , is this the correct way for deferred assertion coverage? . Any inputs ...

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dave_59
dave_59
Forum Moderator
11247 posts
January 04, 2019 at 8:01 am

In reply to sarth21:

There's usually no need to duplicate an asserion directive with a cover directive having the same expression. Tools should automatically treat an immediate assertion as covered if attempted and passing. It should not be part of the coverage computation if never attempted. You may want to check the user manual for your tool for additional information.

You did not provide enough information about your requirements to know if your expression is modelled correctly.

— Dave Rich, Verification Architect, Siemens EDA

sarth21
sarth21
Full Access
22 posts
January 04, 2019 at 11:59 pm

In reply to dave_59:
The assertion expression goes like this : A local counter should be maintainted once a signal enable is present . There is no mention about a particular value it should have so I have not used a clock.therefore I have used an immediate one.
anyway I will look into the tool user manual as you said it should automatically cover .

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