hi , i want to assert using SVA that after a number of rises of a certain signal the output will be high i mean , i want signal (M) to rise ( 9 times for example ) -between each rise it will be zero for some clocks i don’t care about the duration i want to check only that it rises 9 times and then after a clock cycle output flag is high ,i want to write another assertion where the number of rises is signal variable… any help
In reply to bassem yasser:
Typical requirements include a trigger fo the process. Thus,
Folowing a “go”, “m” rises ntimes and tath is folloed by “b”.
// assuming default clocking, n==0
ap_gmb: assert property(
$rose(go) |-> m[->9] ##1 b);
FOr dynamic repeats, see http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
import uvm_pkg::*; `include "uvm_macros.svh"
package sva_delay_repeat_pkg;
sequence dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
sequence dynamic_delay(count);
int v;
(1, v=count) ##0 first_match((1, v=v-1'b1) [*0:$] ##1 v<=0);
endsequence
endpackage
import sva_delay_repeat_pkg::*;
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, m, go;
bit[3:0] n=7;
default clocking @(posedge clk);
endclocking
initial forever #10 clk=!clk;
ap_gmb: assert property(
$rose(go) |-> m[->9] ##1 b);
sequence s_m;
m[->1];
endsequence
ap_gmb2: assert property(
$rose(go) |-> dynamic_repeat(s_m, n) ##1 b);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy