Correct syntax to disable the concurrent assertion on its first failure

SystemVerilog
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1

Hi,

I have a concurrent assertion and want to disable it by virtue of its name on its first failure as it would same my log from same repetitive failing assertion. I have gone through some of the posts available in the verification academy forums, which uses “$assertoff” statement in the else block. Do I need to specify the entire hierarchy of the assertion or just the assertion name is sufficient for disabling the particular assertion? consider the assertion is located in the following hierarchy., testbench_top.module_A.module_B.frequency_check1

For example,

property freq_check(logic disable_cond, inp_sig, time exp_val1, exp_val2);
realtime t;
disable iff(disable_cond ===1’b1)
@(posedge inp_sig) (1’b1, t=$realtime) |=> (($realtime-t)<=exp_val1 && ($realtime -t) >= exp_val2);
endproperty : freq_check

frequency_check1: assert property ( freq_check( reset ,clk, 501ns, 499ns)) else $assertoff(0,frequency_check1);

or Do I need to mention the complete hierarchy like "else $assertoff(0,testbench_top.module_A.module_B.frequency_check1); ?

2

In reply to praveen1705:

The assertion control tasks take a scope that is relative to where the task call is placed. So either way will work.

Also, most tools have ways to automatically limit the number of assertion fail messages. Check your tool’s User Manual.

3

In reply to dave_59:

what $assertoff(0,testbench_top.module_A.module_B.frequency_check1); // what 0 indicates here?