Controlling coverage on assertions

SystemVerilog
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1

Hi, I have a configurable DUT and I have some assertions which check optional features of the DUT. I have mapped the assertions against the requirements and they appear fine in QuestaSim’s Tracker window for configurations with that feature. For those without that feature, they appear as uncovered, because the assertions exist but never start. How do I get them “covered” in those cases?

For coverpoints, I can set the coverage expectations from within my test or environment by setting opitions.goal to the desired value. Is there an equivalent for assertions?

I could modify the verification plan depending on the configuration of the DUT, but I’m not perticularly keen on doing that.

Thanks for any help!

2

The only thing you can do is generate them away, but this only works if the configuration is static (i.e. not changing due to input signals, register values, etc.).