Controlling assertions with scopes defined by a string

Is there any way to control assertions with scopes defined by a string?
e.g.:

string rtl_path = “top_tb.top_rtl_path”;
$assertcontrol(4, 31, 7, 0, rtl_path );

The code above will not work. Is there another way to disable assertion using string?

Thanks,
Dmitriy

In reply to shuruns:

You can’t use strings to access hierarchical paths from within the SystemVerilog language. Most tools provide access via the command line by disabling certain optimizations. Check your tools User Manual or contact them directly for support.