"continuous force" for an internal signal

Hi,

I want to connect an interface output to a verilog internal signal (= forcing the internal signal).
How do you recommend to do this? I don’t want to use “force” inside the environment or interface, but only when connecting the interface to the dut. If there was some kind of “continuous force” (like assign) command it would be great, but I’m not aware of such.

Thanks,
Dana

In reply to danaso:

You need to explain why you can’t use the ‘force’ statement. You can use a force statement to force a DUT signal from an interface. Why won’t this work?

In reply to cgales:

I want to avoid a "force " from the interface. Also it’s a VIP interface and I cannot change it.

In reply to danaso:

You can use a force statement in your top-level testbench module:


module testbench();
  vip_if my_if();

  dut my_dut();

  initial begin
    force my_dut.dut_signal = my_if.if_signal;
  end
endmodule

In reply to cgales:

Thanks! I was under the impression that “force” is not continuous and I have to reforce every time the interface signal is changed, but I see the initial force you suggested is working.