Continuous assignment not updating value when it is changed from 0 to 1

SystemVerilog
,
1

Here’s the code:

module top;
  wire [2:0] win;
  
  assign win = 2'b100;
  assign #5 win = 2'b011;
  
  initial
    $monitor("%2t, win = %b ", $time, win);
  
  initial
    #10 $display("win = %b ", win);
    
 endmodule

Output:
0, win = xxx
5, win = 0xx
win = 0xx

As expected the value of win should be 011 or 000 and it must be 011 at time = 10. But at t= 10, it’s value is stuck to 0xx.
Can anyone explain the reason behind it ?

2

In reply to Kumar Saurabh:

Both "assign win"s are active after 5 time units. You’re driving both a 0 and a 1 to the same wire, which will of course result in a x value.