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  • Constraints to set 32 bit address to be word aligned and 1Kb in length

Constraints to set 32 bit address to be word aligned and 1Kb in length

SystemVerilog 6468
#System verilog 58 #constraint ... 82
Akhil Mehta
Akhil Mehta
Full Access
15 posts
August 13, 2022 at 5:10 pm

I want to implement the following constraint:

Write constraint to set 32 bit address to be word aligned and 1kb in length.

For the length part, I can use addr.size == 1024 inside my constraint. How to make it word aligned?

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KillSteal
KillSteal
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81 posts
August 14, 2022 at 10:01 am

In reply to Akhil Mehta:

If you look at any number/address in binary, a 4 bits(nibble) aligned address will have the lower 2 bits as 0's, a byte(8 bits) aligned address will the lower 3 bits as 0's and so on.
Hope that helps in writing constraints for address alignment.

FOr hte lenght part, I am confused as you only mentioned one 32 bit address. you will need a start and end address to define length.

saumya thacker
saumya thacker
Full Access
8 posts
August 14, 2022 at 11:47 pm

In reply to Akhil Mehta:

To make address word aligned:

class packet;
  rand bit[31:0] addr;
 
  constraint word_aligned{addr[1:0] == 2'b00;}
 
endclass: packet
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