Constraint solver failure

SystemVerilog
1 
class foo;
    rand bit a;
    rand int x;

    constraint c_test
    {
        x >= (1 + a);
        x <= 10;
    }
endclass

module tb;
    initial begin
        foo bar = new;
        repeat(10) begin
            bar.randomize();
            $display("bar.x = %0d", bar.x);
        end
    end
endmodule

If I am running above code I am getting negative numbers for the bar.x,

bar.x = -2088208539

bar.x = -215028475

bar.x = -498680303

bar.x = -574691074

bar.x = -896506966

bar.x = -1472970799

bar.x = -1343312610

bar.x = -1944336458

bar.x = -2003895586

bar.x = -687962719

looks like there is some issue with constraint solver, due to fact that the value X is constrained based on a, where x is type of int and a is a type of bit.
if I am using casting operator (like x >= int’(1 + a);) the behavior looks okay.
Just wondering does the types are getting consider while solving the constraint… Can anyone help me on the root cause behind this?

2

In reply to Deepak Muduli:

int a 32-bit signed data type that having values from ( -231 ) to ( 231) - 1

So when you constraint x < 10 ;x can have All Negative Values ( -231 to -1 )
plus Values 0 to 9**

3

In reply to Deepak Muduli:

You may want to look at: Verilog Basics for SystemVerilog Constrained Random Verification | Verification Academy

4

In reply to ABD_91:

I agree, but I have mentioned x > (1+a), that should avoid the negative number, correct me if I am wrong.

5

In reply to Deepak Muduli:

Your problem is a is unsigned, so the entire expression is evaluated unsigned. Your cast to an int fixes that.

6

In reply to dave_59:

Thank you, Dave, Got an insight view, how things are working underneath.