Constraint randomization

SystemVerilog
, ,
1

Write a constraint for an array. Two consecutive elements in the array should not differ by more than two bits.

Can someone please help with this question. Thank you

2

In reply to sriharifoxtrot:
Two consecutive can have difference of 0 ,1 or 2 .
// Code your testbench here
// or browse Examples


module top ;
  
  class A ;
    
    rand bit [7:0] a[];
    
    constraint c_a {
      a.size() == 5 ;
      
      foreach(a[i])
        if(i > 0){
          ($countones(a[i]) -$countones(a[i-1]) ) <= 2;
          ($countones(a[i]) -$countones(a[i-1]) ) >= 0;
        }
    }
    
  endclass 
  
  initial begin 
    A a1 = new ;
    a1.randomize();
    foreach(a1.a[i])
      $display("%b",a1.a[i]);
    
  end 
  
endmodule
3

In reply to kddholak:

I think they want

   foreach(a[i])
        if(i > 0)
          $countones(a[i]^a[i-1]) <= 2;