Constraint & Random variable distribution

SystemVerilog
1

Here is something that I do not understand. In the below code, I understand that (a==1) → (b==int’(10)); does NOT mean that the reverse is true. i.e It is not bidirectional.

However, what I do not understand is the skewed distribution of the values of a : Why do we get so little 1’s ? Why the heavy bias towards the 0 ?

module top;

  class foo;
    rand bit a;
    randc bit[7:0] b;  
    int unsigned cntra_0;
    int unsigned cntra_1;
    
    constraint goo_cnstr {
      (a==1) -> (b==int'(10));
    }

    function new();
      cntra_0 = 0;
      cntra_1 = 0;
    endfunction // new
    
    
    function post_randomize();
      if (a==0)
        cntra_0++;
      else
        cntra_1++;
    endfunction // post_randomize

  endclass

initial begin
  foo f = new();

  repeat(100000) begin
    assert(f.randomize());
  end
  
  $display("f.cntra_0:%0d f.cntra_1:%0d", f.cntra_0, f.cntra_1);
end
  
  
endmodule // top

Here is the output I see :
f.cntra_0:99792 f.cntra_1:208

2

In reply to DVJoe:

It is because of this constraint. Out of (2^8) combinations you are expecting b to be 10 when A is 1.

(a==1) → (b==int’(10));

A value = 1 , B value : 00001010

3

In reply to dave_59:

Thanks Dave. That makes sense.