Constraint on randc

SystemVerilog
, ,
1

i am trying to apply constraint on randc variable(value between 3 and 9) as used in code shown below. I have understanding that b_var should generate the cyclic values between 3 and 9. but with three calls of randomization it generates 4,8,6.
Then My question is that:
Applying a constraint on randc variable convertes this to normal rand variable?

class A ;
  rand int a;
  randc bit [3:0] b_var;
  constraint cyc_check;
endclass

constraint A::cyc_check {b_var>3;
                         b_var<9;}
module top;
   initial
    begin
    A a1;
      a1=new;
      assert(a1.randomize());
      $display ("value of b_var=%d", a1.b_var);
      assert(a1.randomize());
      $display ("value of b_var=%d", a1.b_var);
      assert(a1.randomize());
      $display ("value of b_var=%d", a1.b_var);
      end
endmodule

############### OUTPUT ################

run -all;
# KERNEL: value of b_var= 4
# KERNEL: value of b_var= 8
# KERNEL: value of b_var= 6
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit
2

What values were you expecting?

The solution space are the values 4, 5, 6, 7, and 8.

So that means you need to call randomize() 5 times before any value repeats.

3

In reply to dave_59:

Thanks for clarification. I could see expected results after repeating 5 times.