Constraint question

SystemVerilog
1

I want a variable to randomize to a static value most of the time, and occasionally any other value (besides that constant).

I.e.
99%: ==constant
1%: !=constant

constraint c_ip { ip dist {'hAD_18_18_14:=20, ???:=1}; }
2

In reply to bmorris:
Use an implication

rand bit mode;
constraint c_ip {mode dist {1:=99, 0:1};
                 mode -> ip_dist == 'h12345678;
                 solve mode before ip_dist; }
3

In reply to dave_59:

This also works as a one line:


constraint c_ip { ip == 'h12345678 dist { 1:=99, 0:1 }; }

Plus, in your code you have the case that when mode is 0, you can still get 'h12345678. Technically, you’d need double implication.

4

In reply to Tudor Timi:

That also seems to work. I’ve not seen this syntax before… do you have any ref material that talks about this?

5

In reply to Tudor Timi:

Hello Tudor

Could you please provide the small desription of this syntax as I have not seen before ?

Thanks,
Kapil

6

In reply to bmorris:

In section 18.5.4 Distribution of the LRM, the BNF states:

expression_or_dist ::= expression [ dist { dist_list } ]

expression can be any legal constraint expression, not just a variable.

7

In reply to Tudor Timi:

So it is… I generally ignore the Backus–Naur syntax descriptions because I couldn’t read them. I guess I’ll learn it now. :p