Constraint for packed array

SystemVerilog
1

i want to write a constraint such that address should be increment like following {0,4,8,c,10,14,…};
rand bit [15:0] addr;

2

In reply to subbarao:

In reply to subbarao:

That is not a random sequence of values. You could do this with post_randomize:

class C;
  bit [W:0] addr = -4;
  function void post_ranmdomize;
    addr +=4;
  endfunction
endclass
3

In reply to dave_59:

hi dave, can you please look into this issue. I am unable to generate the addresses even after adding logic in post randomize function.

4

In reply to subbarao:

Big difference between
addr += 4; and
addr =+ 4;.