Constraint for Octal Addition

SystemVerilog
,
1

Consider the following code ::


module top;

   class oct ;
     
     rand bit [3:0] s , e , n , d , m , o , r , y ;

     constraint  elem { s inside { [1:7] } ; m inside {[1:7]} ; 
                      
                        e inside { [0:7] } ; n inside {[0:7]} ;  
                       
                        d inside { [0:7] } ; o inside {[0:7]} ; 
                       
                        r inside { [0:7] } ; y inside {[0:7]} ; 
                      }    
     
     
     constraint  UNIQ  {  unique   { s , e , n , d , m , o , r , y  } ;  }

    //   Requirement  ::  SEND  +  MORE  ==  MONEY

     constraint  sum  {  ( 512*s + 64*e +  8*n + d )  +  
                       
                       (  512*m + 64*o + 8*r + e )  ==  ( 4096*m + 512*o + 64*n + 8*e + y ) ;  }
       
   endclass
 
   oct h;
   
  initial begin
    
      h = new;
       
    repeat(2)

      if( h.randomize() ) begin

        $display(" send   is   %0d_%0d_%0d_%0d " , h.s , h.e , h.n , h.d );
        $display(" more   is   %0d_%0d_%0d_%0d " , h.m , h.o , h.r , h.e );
        $display(" money  is  %0d_%0d_%0d_%0d_%0d " , h.m , h.o , h.n , h.e , h.y );  
       
      end  
 
  end
endmodule : top

I observe constraint failure . Is it because of the solution space doesn’t exist OR am I missing out on anything ?

2

In reply to MICRO_91:

You are missing out on the error message that tells you there is no solution.

If you think there is a solution to this, set the variables to the values you think should satisfy the constraints and then call h.randomize(null).

I’m pretty sure there is no solution to this without m=0.