Constraint on int type variable is not working as expected

SystemVerilog
1

Output -
Int array = '{86981979, 584823717, 388759772, 1607847894, 928990077, 1009032424, 1426036090, 2133673444, 233211323, 190577892} Sum = 20

If I manually sum the array elements printed above I see that the lower most bits have the value of 14 in HEX (20 in decimal).
Please help me understand why the array elements are having huge values.

class constraint_on_int_array;
  rand int int_arr[10];
   
  constraint c1 { int_arr.sum == 20;}
  constraint c2 { foreach(int_arr[i]) int_arr[i] > 0;}
   
  function void display();
    $display("Int array = %p Sum = %0d", int_arr, int_arr.sum);
  endfunction
   
endclass
 
module tb;
  constraint_on_int_array p;
 
  initial begin
    p = new();
    p.randomize();
    p.display();  
  end
endmodule
2

In reply to naveensv:

When you sum your numbers, you are overflowing the 32bit integer size.

You should constrain each element to be less than 20:


constraint c2 { foreach(int_arr[i]) int_arr[i] inside {[0:20]};}
3

In reply to naveensv:

See http://go.mentor.com/verilog-in-constraints

4

In reply to cgales:

Yes, the hex value of sum is 2_0000_0014.

Thank you!

5

In reply to dave_59:

Great article, Dave!
" For all arithmetic operators the result width is the size of its largest operand, not the width of the largest possible result which would be 34 bits in this case. "

Thanks.