Constraint inside {packed array.index==1}

SystemVerilog
1

Hi,

I have an index register and a vriable,
I want to constraint the variable to be inside rised bits in the index register.

let say I have 30 children in the class and I want to choose one child only if is at school today,
so I have

logic [29:0] children_at_school_today;
logic [5:0] choosen_child;

if today at school are childrens [2,3,4,5,6,12,13,14,15]
children_at_school_today = 30’b1111000001111100;
and what I want is a constrait that return a number inside [2,3,4,5,6,12,13,14,15]
how can I implement such a constraint.

Thanks

2

In reply to rraa:

module top;
class C;
  logic [29:0] children_at_school_today =  30'b1111000001111100;
  rand logic [5:0] choosen_child;
  constraint pick_one { (children_at_school_today >> choosen_child)%2 == 1'b1; }
endclass
C c=new;
  initial repeat(10) begin
    assert(c.randomize);
    $display("choosen_child: %d",c.choosen_child);
  end
endmodule
3

In reply to rraa:

This could be another possible solution!


  class check;
    
    rand bit[31:0] children_at_school_today;
    
    rand bit [5:0] choosen_child;
    
    
    constraint value_c {  children_at_school_today[choosen_child] ==1;}
    
  endclass