A constraint to generate odd_even_odd....... etc sequence

SystemVerilog
, ,
1

I need to write a constraint to generate a sequence that toggle between odd and even states.


program blk; 
class test;  
  rand bit [7:0] x;
  
  endclass : test
  
  initial begin
    test t1;
    repeat(10);
    void'(t1.randomize()); 
    
  end
  
endprogram
2

In reply to Omran:


 import uvm_pkg::*; `include "uvm_macros.svh" 
module blk; 
class test;  
  rand bit [7:0] x;
  bit w;
  constraint c1 {x%2==w;}
endclass : test
 
  initial begin
    test t1=new();
    repeat(10) begin;
      // void'(t1.randomize()); 
      // BETTER methodology 
      if (! t1.randomize()) `uvm_error("MYERR", "This is a randomize error")
      t1.w= !t1.w;
      $display("t1.x=%h", t1.x);
    end
  end
endmodule 
t1.x=b4
t1.x=91
t1.x=24
t1.x=1d
t1.x=64
t1.x=b5
t1.x=14
t1.x=27
t1.x=4c
t1.x=ef

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home

3

In reply to ben@SystemVerilog.us:

Thank you!

4

You can also use const’ in the constraint, which gives the previously randomized value.


class packet;
    rand bit [7:0] x;

    constraint c {(x % 2) != (const'(x) % 2);};
endclass : packet

module tb;
    packet packet_h;

    initial begin
        packet_h = new;

        repeat (10) begin
            if (!packet_h.randomize) $finish;
            $display ("x = %b", packet_h.x);
        end
        $finish;
    end
endmodule : tb
5

In reply to sbellock:

Hello Sbellock,

I am getting a compilation error in the line where you have const’.

Can you plz check and correct it?

6

In reply to puttasatish:

In reply to sbellock:
Hello Sbellock,
I am getting a compilation error in the line where you have const’.
Can you plz check and correct it?

It compiles fine in Questa. If it’s not a syntax error on your side then you should consult with your simulator vendor about it.

7

In reply to sbellock:

Maybe it’s a tool thing, but in Edit code - EDA Playground
I get an error with Incisive and CVS.
In this forum we want to avoid talking about tools.
My first solution avoids this const’ thing,
I agree, the const’ thng is “elegant”, but use what makes it work.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

8

In reply to ben@SystemVerilog.us:

Hmm looks like I’ve been using it willy-nilly, even though it might not be explicitly in the LRM. See Dave’s comment on this mantis item.

9

In reply to ben@SystemVerilog.us:

Hi Ben,

Your code looks perfect but here, user needs to take care toggling of “t1.w” each time after calling randomization. So I teaked your code and modified as below. Please let me know if below code has any side effect,


program blk; 
class test;  
  rand bit [2:0] x;
  // odd_even bit to indicate whether siganl should be odd or even after randomization
  // odd_even == 1 then even data generated
  // odd_even == 0 then odd data generated
  static bit odd_even;
  //pre_randomize function will be called every time before randomize function
  function pre_randomize();
    $display("Inside pre_randomize");
    odd_even = ~odd_even;
  endfunction
  
  constraint cons{
    (odd_even == 1) -> x%2 == 0;
    (odd_even == 0) -> x%2 != 0;
  }
  endclass : test
 
  initial begin
    test t1;
    repeat(10) begin
      t1 = new();
      void'(t1.randomize()); 
      $display ("t1.x = %0d t1.odd_even = %0d", t1.x, t1.odd_even);
    end
  end
 
endprogram

@Omran,
Above code will randomize signal in class itself. Please let me know if it works for you.

Regards,
Priyank
Tel: +917939330000 | Cell: 8347036353
Product Engineering Services
Software | System | Silicon | Mechanical
www.einfochips.com | priyank.agrawal@einfochips.com

10

In reply to Agrawal Priyank:
This works for me, BUT with some minor mods.

  1. I like the use of the pre_randomize
  2. Tool recommended use of void in the function
  3. Use module instead of program. There are many many discussions in this forum on why you should NOT use the program. SEE
    Verification Horizons - Siemens Software
  4. It is not a good methodology to use
void'(t1.randomize()); 
//Instead, use something like 
if (! t1.randomize()) `uvm_error("MYERR", "This is a randomize error")
// Modify your uvm_erro tag and message as you see fit

Simulated model available at


import uvm_pkg::*; 
`include "uvm_macros.svh" 
module blk; 
class test;  
  rand bit [3:0] x;
  // odd_even bit to indicate whether siganl should be odd or even after randomization
  // odd_even == 1 then even data generated
  // odd_even == 0 then odd data generated
  static bit odd_even;
  //pre_randomize function will be called every time before randomize function
  function void pre_randomize();
    $display("Inside pre_randomize");
    odd_even = ~odd_even;
  endfunction
 
  constraint cons{
    (odd_even == 1) -> x%2 == 0;
    (odd_even == 0) -> x%2 != 0;
  }
endclass : test
 
  initial begin :i
    test t1;
    repeat(10) begin : r
      t1 = new();
      // void'(t1.randomize()); // NOT A GOOD STYLE
      if (! t1.randomize()) `uvm_error("MYERR", "This is a randomize error")
      $display ("t1.x = %0d t1.odd_even = %0d", t1.x, t1.odd_even);
    end : r
  end : i
 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home