Constraint for error injection

SystemVerilog
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1

Hi ,

I have following scenario, need to get a constraint for that.

There is array of 1000 bits, 10 errors has to injected with following condition.

  1. the error injected in to 1000 bits should not be cyclic. Example:: if error is at bit 2, next error should not be at 3 so on.
  2. All the 10 error injected should have unique errors patterns.

Thanks

2

In reply to syed taahir ahmed:

Your question is not clear. What is an error? Dou you mean to say you have a pattern of 1000 bits and you want a random 10 of the bits inverted?

Instead of cyclic, do you mean consecutive?

What makes an error pattern unique?

3

Hi Dave,

Yes it’s like a error frame generation, 10 errors to generated with each error being unique.
Yes the error bits inserted should be random for each error not on consecutive Index.

I hope this gives little clear picture.

Thanks

4

In reply to syed taahir ahmed:
What makes an error pattern unique?

5

In reply to dave_59:

Insertion of error bits to the fixed 1000 bit frame makes it different for each.
Totally 10 Errors, so each error is nothing but Frame of 1000 bits + Error bits injected. Error bits should not be injected consecutively.

For example:: in Error 1 pattern, 1000 bits are injected with 5 error bits which are not consecutive.
In error 2 pattern, 1000 bits are injected with 7 error bits , and so on

6

In reply to syed taahir ahmed:

OK, now you are a little bit clearer, but still a lot of missing information. Let’s create an array of bits indicating which bits in your pattern should have an error

bit [0:999] pattern;
rand bit error_bits[1000]; // bit set if inject error

You never stated what an error looks like, but I will assume an error is an inverted bit. You can generate the errors with this in post_randomise();

foreach (error_bits[b]) pattern[b] ^=error_bits[b];

You want to inject N error bits into a pattern of 1000 bits. You never specified how many bits out of those 1000 could have an injected error, but let me assume a range from 1 to 100. You constraints would then look like

constraint c {
     error_bits.sum() with (int'(item)) inside {[1:100}; // number of bits that will have an error
     foreach (error_bits[b]) b>0 -> !error_bits[b] || !error_bits[b-1]; // no consecutive errors
      foreach (error_bits[b]) const'(error_bits[b]) -> !error_bits[b];  // no repeated errors
}

You need to repeatedly call randomize() 10 times to get 10 error scenarios.

7

In reply to dave_59:

Hi Dave,

Thanks for your response, almost the logic is matching with the needs.
I tried with your logic , seems like casting is not working in constraint.

Below is playground link i tried::

Could you please have a look.

Thanks

8

In reply to syed taahir ahmed:
Works in my simulator. const casting is a relatively new feature of SystemVerilog and the simulator on EDAPlayground are older. See Constraint | Verification Academy

9

In reply to dave_59:

Thanks Dave , I’ll have a look