Constraint to cause a value to be within a set defined in a dynamic array

SystemVerilog
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1

I am trying to write a constraint that will cause a variable to be selected from a set of predefined values. This would only occur when another bit is set to true so I would like to place it within an implication. If valid_transaction is not true then any value can be picked.

I have sketched out the following pseudo-code.

byte set_of_values [6] = {'h3, 'h6, 'h7, 'h9};

rand bit valid_transaction;
rand byte my_value;

constraint valid_c {
valid_transaction → my_value inside {set_of_values};
}

The part that I can’t get to compile is the “my_value inside {set_of_values}”. Is there a valid syntax to cause my_value to take on one of the values in set_of_values? Or do I need to take a slightly different approach?

Thanks.

2

In reply to paul_mckechnie:

You are declaring set_of_values with a fixed size of 6, yet you are trying to initialize it with an array of 4 values. You need to change the size of something, or you can declare it as a dynamic array, set_of_values. When you reference the array, do not use any 's.

Also realize that valid_transaction only has a 4/256 = 1.6% chance of being set.
https://verificationacademy.com/forums/systemverilog/constrain-random-variable-result-enumerated-type#reply-48832