Constraint addition of array element without using array.sum() method

SystemVerilog
1

Hi,

Is there any way by which we can constraint addition of array element without using sum() inbuilt method?

I tried below code but not working. Any suggestion ?

class c;
  rand logic [7:0] a [];
  constraint array_size {a.size() == 10;  }
    constraint array_items { 
      foreach(a[i]) a[i] < 10;
        
    }
 
  constraint sum_array_c {a_sum() == 10; }
  
    function int a_sum();
      a_sum = 0;
      foreach(a[i]) 
        a_sum += a[i] ;
 
    endfunction 
  
 
endclass
 
module test;
   initial begin
      c c1 = new();
 
      void'(c1.randomize());
 
     foreach(c1.a[i])
        $display("%0d ", c1.a[i]);
 
   end // initial begin
endmodule // test

I see below error:

testbench.sv(25): randomize() failed due to conflicts between the following constraints:

testbench.sv(9): sum_array_c { (this.a_sum() == 10); }

Where:

this.a_sum() = 0

2

In reply to niravshah:

Your classmate beat you to the same question. Can I constrain a sum/function of array element sizes? | Verification Academy

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