Constraint 80% times addr is greater than a certain value and 20% times it's less

SystemVerilog
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1

I want to know why below code show only 0 & 1 ???


constraint c1{
    addr dist {(addr > 45):= 80,(addr < 45):= 20};
  }

For full code : constraint 80 to 20 value - EDA Playground

But below one work properly


constraint c1{
    addr>45 dist {1:= 80,0:= 20};
  }

For full code : (1) - EDA Playground

In both constraint logic are right but first one constraint show only 1 & 0

2

In reply to amir_sharfu:

A dist constraint also behaves like a set membership inside operator constraint. The value on the LHS must be in the set of values on the RHS.

In your second constraint, the set of values on the RHS are 0 and 1, and the possible values on the LHS expression can only be 0 or 1. So this constraint does not constrain any values, just affects their distribution.

In your first constraint, the expressions on the RHS can only result in a 0 or 1, so that means the value on the LHS is constraint to only be 0 or 1. So addr can only be 0 or 1. It’s distribution does not make any sense.