Constraint

SystemVerilog
1

// Code your design here

module main();

class mainn;       

  rand int a [];
 static int count;

  constraint c1 { a.size ==20;}
  constraint c2 { foreach(a[i])
   							 if(i%2==1)
							      a[i]==0;
                                                      else if(i%2==0)
                                                         a[i] == even;}

  function int even ;
count=count+1;
  even=count;
endfunction
endclass

initial
begin
mainn p=new();
begin
p.randomize();
  $display("A==>%p ",p.a);
end
end
endmodule

expected output is a==>{1,0,2,0,3,0,4,0,5,0,6,0,7,…}
actual output is A==>'{20, 0, 19, 0, 18, 0, 17, 0, 16, 0, 15, 0, 14, 0, 13, 0, 12, 0, 11, 0}
iam unable to find out the bug.

2

In reply to vijayguptavg:

Please use code tags making your code easier to read. I have added them for you.

A couple of problems with your code. The first is that foreach is an iterative constraint. It gets unrolled into 20 concurrent constraints with i replaced with the constant values 0…19. You cannot rely on the order the constraints get evaluated on.

The other problem is you are calling a function that is not pure, meaning its output is not solely determined by its inputs. In fact it has no inputs other than an external state variable. maybe you should replace even with (i/2)+i.

3

In reply to vijayguptavg:

module main();
 
class mainn;       
 
  rand int a [];
  static int count;
 
  constraint c1 { a.size ==20; }
  
  constraint c2 { foreach(a[i])
    		  if(i%2==1) a[i]==0;
                  else if(i%2==0) a[i] == int'((i+2)/2);
                }  
endclass
 
initial
begin
  mainn p=new();
  begin
    p.randomize();
    $display("A==>%p ",p.a);
  end
end
  
  
endmodule