Constraint

SystemVerilog
,
1

Write a SystemVerilog constraint for a number when it is even the probability of occurrence of that number is 80% and when it is odd the probability of occurrence of that number is 20%.

2

In reply to Abhijeet Anand:



class odd_even;
  rand bit [3:0] test;
  
 
  //Write a SystemVerilog constraint for a number when it is even the probability of occurrence of that number is 80% and when it is odd the probability of occurrence of that number is 20%.
  
  constraint odd_even {
    test[0] == 0 dist {0:=20,1:=80}; 
  
  }
  
endclass
 
module top;
 
  odd_even oe=new;
  initial repeat(100) begin
    assert(oe.randomize());
    $display(oe.test);
  end
endmodule