Constraining the columns of a Matrix

SystemVerilog
, ,
1

Hello all,

I have a matrix that I am trying to put constraints on

my conditions are:

  • for each row, # of 1’s is >=1;
  • for each column, # of 1’s = 1;
    I did:

  bit [X-1][Y-1] matrix;
  constraint matrix{
    foreach(matrix[i]){
      $countones(matrix[i])>=1;
    }
   //Here I need a foreach to loop through the columns and make sure the countones ==1, I'm 
   //just not sure of the correct syntax to use.
  }

Thank you!

2

In reply to Fa300:

See 2-Dimenson Dynamic array Constraints | Verification Academy

3

In reply to dave_59:

Hello, that solution does not work in my case since I am using a packed array. Is there any other solution you can suggest?

4

In reply to Fa300:

You can still use that solution by creating another unpacked array, and setting the following constraint;

rand bit [X-1:0][Y-1:0] packed_matrix;
rand bit unpacked_matrix[X][Y];

constraint matrix_equivalent {
   foreach(unpacked_matrix[x,y]) unpacked_matrix[x][y] == packed_matrix[x][y];
}
constraint matrix_col {
    foreach (unpacked_matrix[,j]) unpacked_matrix.sum() with (int'(unpacked_matrix[item.index][j])) == 1;
  }
5

In reply to dave_59:

Hello Dave!

What is with the ,j in the foreach loop? How does it work?

Thanks!

6

In reply to Shashank Gurijala:

j iterates from 0 to Y-1.

7

In reply to dave_59:

Then why not use just j instead of ,j in the foreach loop?

8

In reply to Shashank Gurijala:
Because then j iterates from 0 to X-1.