In reply to dave_59:
Thank you, Dave, for your response.
Sorry for not indicating that I was using UVM. I did want to see if there was any solution without UVM.
Okay, I read the paper and seen the example. I see that for the probe interface do you use the port fashion, in UVM I have only seen class members, so I was wondering, it would be possible to use class members for the signals that I don't want to probe (I will stimulate them in the driver with the sequences) and the ports of the interface for the signals I want to probe?