Connecting port to higher width wire in verily

SystemVerilog
,
1

I have a module where the output is 4 bit wide. I have an interface which is common and I am binding the interface inside the module.
The signal in the interface is 8 bit wide.

Sample snippet below:

module A(output wire [3:0]o);
assign o = 4'b1010;

endmodule
module test;
wire [7:0] a;
A A1(.o(a));
initial begin
#1 $display("Value of a: %b",a);
end
endmodule

Different simulators are behaving differently.
vcs output:V alue of a: 00001010
Incisive output:Value of a: zzzz1010

what is the actual expected output according to LRM?
when we assign the lower width signal to higher width signal, is simulator expected to do zero expansion on the MSB side?

2

In reply to Venkateshwara Rao:

According to section 10.8, a port connection to an input or output port of a module, interface, or program is consider an assignment like context. So as unsigned typed ports, it should 0-extend.

However, the LRM makes a special exception (23.3.3.7 Port connections with dissimilar net types (net and port collapsing)) for net connected to other nets, and that appears to be optional. All other cases are treated like a continuous assignment context.

Basically, the SystemVerilog committee could not reach a consensus and gave up making it undetermined.