In reply to Venkateshwara Rao:
According to section 10.8, a port connection to an input or output port of a module, interface, or program is consider an assignment like context. So as unsigned typed ports, it should 0-extend.
However, the LRM makes a special exception (22.214.171.124 Port connections with dissimilar net types (net and port collapsing)) for net connected to other nets, and that appears to be optional. All other cases are treated like a continuous assignment context.
Basically, the SystemVerilog committee could not reach a consensus and gave up making it undetermined.