Connecting multiple instances of interface with multiple clock

SystemVerilog
,
1

Hi

I have the following code which is working fine as written.

module tb;
  import my_pkg::*;
  parameter num_inst=2;
  bit clk;
  bus if_[2](clk); //driving both instances with a single clock
  dut d1(if_[0],if_[1]); //**can I also write this in terms of num_instance where num_instance is 2?**
  env e;

  for(genvar i=0;i<2;i++) begin
      initial uvm_config_db#(virtual bus)::set(null,"*",($psprintf("drv[%0d]",i)),if_[i]);
  end
  initial begin
    e=env::type_id::create("e",null);
    run_test();
  end
  initial begin
    clk=0;
    repeat(100) begin
      #5 clk = ~clk;
    end
    #100 $finish();
  end
endmodule

I want to drive the different instances with different clock, let’s say I have a variable

bit clk[num_ins]

. How can I declare an interface and connect the clock in that scenario without changing the interface? The interface definition is-

interface bus (input bit clk);
  logic srdy;
  logic rrdy;
  clocking cb @(posedge clk);
    output srdy;
    input rrdy;
  endclocking
  clocking cb_mon @(posedge clk);
    input srdy;
    input rrdy;
  endclocking
  modport DUT(input clk, input srdy, output rrdy);
endinterface
//and dut is something like
module dut(bus.DUT if1, bus.DUT if2);
  assign if1.rrdy = 1;
  assign if2.rrdy = 1;
  always @(posedge if1.clk) begin
    if(if1.srdy && if1.rrdy) $write("interface1 ");
  end
  always @(posedge if2.clk) begin
    if(if2.srdy && if2.rrdy) $write("interface2 ");
  end
endmodule

Thanks!

2

In reply to possible:

If you change the clock from an unpacked to packed array, you can do

bit [0: num_ins-1] clk;
bus if_[2](clk); // clk[0] goes to if_[0] and clk[1] goes to if_[1]

Or you can use a generate loop instead of an array of instances

for(genvar i=0; i<num_ins;i++) begin: block
  bus if_(clk[i]); // clk[0] goes to block[0].if_ and clk[1] goes to block[1].if_
end