Connecting 2-D signal in testbench

SystemVerilog
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1

Which is the correct way to connect a 2-D signal in the port connection of a testbench. For the DUT shown below, how to connect a signal to signal_2d_out in testbench to view the output?

module dut(
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.
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output logic [7 : 0] signal_2d_out [99 : 0];
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2

You can either connect the signals in one of the three ways:

  1. Port connection by position
module top();
  logic [7 : 0] signal_2d_out [99 : 0];
  dut d1(signal_2d_out); // By position
endmodule
  1. Port connection by name
module top();
  logic [7 : 0] signal_2d_out [99 : 0];
  dut d1(.signal_2d_out (signal_2d_out)); // By .name
endmodule
  1. Using implicit port connection
module top();
  logic [7 : 0] signal_2d_out [99 : 0];
  dut d1(.*); // Implicitly connect port
endmodule

You can also connect slices of port to different signals like follows:

module top();
  logic [7 : 0] sig_1 [99:50];
  logic [7 : 0] sig_2 [49 : 0];
  dut d1(.signal_2d_out ({sig_1,sig_2})); // By .name connect slices
endmodule