Hi,
I have a VHDL DUT, which defines the following type:
type my_vhdl_type is array(natural range <>) of std_logic_vector(31 downto 0);
the DUT top level entity uses this type a one of its input ports:
my_vhdl_port : in my_vhdl_type(0 to 3);
in my SystemVerilog interface, I defined the following:
logic [31:0] my_sv_signal [0:3];
and connected it to the DUT in the top module:
.my_vhdl_port(u_interface.my_sy_signal),
this does not work - it causes elaboration error(I use Questa 2019.2 64 bit for Linux):
Fatal(vsim-3362) the type of the VHDL port my_vhdl_port is invalid for verilog connection.
Can you please reply with a working example?
Thanks
Have you tried a shared package ?
I tried the following code in my_pack.vhd
*******************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_pack IS
TYPE array_t IS ARRAY (2 DOWNTO 0) of STD_LOGIC_VECTOR(2 DOWNTO 0);
TYPE my_vhdl_type is array(natural range <>) of std_logic_vector(31 downto 0);
END PACKAGE;
*******************
Then my SV code was as follows:
Note that it imports the VHDL package and uses the same type name ‘my_vhdl_type’
`define N_PORTS 3
`define N_CHANNELS 4
import my_pack::*;
module pwr_ctrl(
input logic clk, rst_n,
input array_t channel_addr_i,
input my_vhdl_type dummy_port[0:3],
input logic [`N_CHANNELS-1 : 0] transaction_complete_i,
output logic [`N_CHANNELS-1 : 0] sleep
);
endmodule
*******************
Then my VHDL code uses he same package
LIBRARY WORK;
USE WORK.my_pack.ALL;
it declares a signal of the type for connecting to the SV component
signal dummy_sig : my_vhdl_type(0 to 3);
and instantiates the SV component & connects the signal
power_ctrl : pwr_ctrl
port map(
clk => aclk,
rst_n => aresetn,
dummy_port => dummy_sig,
channel_addr_i => ch_addr,
transaction_complete_i => transaction_complete_i,
sleep => sleep
);
When compiling the VHDL package you must use the -mixedsvh switch
vcom -mixedsvvh my_pack.vhdl
vlog pwr_ctrl.sv
vcom vhdl_top.vhd
vsim -voptargs=“+acc” vhdl_top
Compiles and loads for me using Questa 10.7d