Confusion with rand

I am trying to understand how rand exactly works in system verilog hence I wrote following code :

class A;
  //rand bit[2:0] a, b, c;
  bit[2:0] a, b, c;
  
  function new();
    $display("New of class A");
  endfunction
  
  function void display();
    $display("class A %0d %0d %0d", a,b,c);
  endfunction
endclass

class B;
  rand A Ba;
  
  function new();
    $display("New of class B");
    Ba = new();
  endfunction
  
  function void display();
    $display("class B %0d %0d %0d", Ba.a,Ba.b,Ba.c);
  endfunction
endclass

module top;
  initial begin
    A a;
    B b;
    bit check;
    
    a = new();
    check = a.randomize();
    $display("check = %0d", check);
    a.display();

    b = new();
    assert(b.randomize());
    b.display();
  end
endmodule

Got output :
New of class A
check = 1
class A 0 0 0
New of class B
New of class A
class B 0 0 0

Output of class makes sense all 0’s.
However I was expecting atleast in class B all variables are randomized.
I think I might have seen B being randomized in UVM testbench.

if i declare variable in class A as rand both A and B objects are randomized.(uncomment the line after class A)

Can someone explain this ?

The 2017 LRM states that:

An object handle can be declared rand, in which case all of that object’s variables and constraints are solved concurrently with the variables and constraints of the object that contains the handle. Randomization shall not modify the actual object handle.

However, there’s this issue that dates from 2006 which states that:

Section 13.3 “Random variables” is not specific that only “rand” variables in a “rand” handle class are to be randomized. Also, it’s not clear if “rand” variables in non-rand handles and structs are to be randomized.

where section 13.3 is now 18.4. Apparently this is an LRM bug that needs to be fixed. However, it has survived through the 2009, 2012, and 2017 updates.

In reply to sbellock:

Thanks @sbellock.
One thing I realized after few runs is that rand won’t mean anything for class until its member variables are declared rand.