Configuration class

Hi everyone!
I make a verification testbench and i have some troubles about DUT configuration. My DUT it’s an SPI MASTER conttroled with wishbone interface. Ok… My first ideea it’s was about configuration at the beggining of the test. How can i make an configuration class in systemverilog? The configuration it’s maked throught wishbone driver? Can you make an overview about DUT configuration ? Yeah, many questions… Thanks a lot!

In reply to andrei.toderita:

https://verificationacademy.com/cookbook/configuration

Thanks a lot Dave!!

In reply to dave_59:

Dave, I have another question for you. Ok… When the drive don’t driving the whisbone interface, can I put the si****gnals from driver in high z ? It’s Ok? My first argument it’s based on the interface usseles. The interface it’s used between many divices who can driving an signal(ex : wb_we )and if are 2 devices who driving together.
Example : one device driving wb_we = 1, and anothe driving wb_we = 0. It can produce an short to ground.
I mention something about my DUT. My DUT in my testbench it’s drives only with one driver.

In reply to andrei.toderita:

Yes, that’s assuming your Wishbone is using a 3-state bus topology.