Configuration class

SystemVerilog
1

Hi,

Where can I read up about the configuration class in system verilog and its usage/example? Not w.r.t UVM but just systemverilog. Basically, if before UVM, how was the configuration of objects deep down in the hierarchy done using configuration class?

Thanks.

2

In reply to UVM_beginner:

You could use global variables for everything, but that gets very messy as your environment grows and you start needing multiple sets of global variables.

There’s no single good answer to this question. The UVM is just SystemVerilog code and they have picked one way of dealing with configuration.

3

In reply to dave_59:

Ok thanks. So I understand from your reply, that all the configurable variables were declared global and set up/changed inside the configuration class?

If there is any link that has an example of this, please share.

Thanks for your time.

4

In reply to UVM_beginner:

Sorry I won’t do that. The point of UVM is to standardize on a verification methodology. You can always borrow from UVM even if you don’t want to adopt it entirely.