Concurrent Assertion :: Sig asserted for N Clocks V/S Signal Asserted on N Clocks

Hi all ,

I was trying to understand following 2 scenarios ::

(a) Sig once asserted , remains asserted FOR ‘N’ Clocks

(b) Sig once asserted , remains asserted ON ‘N’ Clocks

I tried following Code :: EDA_LINK

Can I say that ::


"Sig  remains  asserted  on  N  clocks "  is  equivalent  to  saying  "Sig  remains  asserted  for  ( N - 1 ) clocks "

Eg :: If Sig is sampled high for 1 Clock period of the Sampling clock , I can say ::

Via “on” :: Sig is asserted on 2 clocks whereas

Via “for” :: Sig is asserted for 1 clock .

In reply to hisingh:
English has its inflections and ambiguities. Your requirements needs to be expressed more clearly: Thus, write
(a) Sig once asserted , remains asserted FOR ‘N’ moreClocks

(b) Sig once asserted , remains asserted ON for ‘N’ moreClocks
N is an unsigned number, and can be 0.

@( posedge clk ) $rose( Sig ) |-> Sig[*numClk + 1 ] ;

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

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In reply to ben@SystemVerilog.us:

Hi Ben ,

Do you mean that the following 2 are same ::

(a) Sig once asserted , remains asserted FOR ‘N’ more Clocks

(b) Sig once asserted , remains asserted ON for ‘N’ more Clocks

And  the  Check  for  the  same  can  be  written  as  ::

    @( posedge clk ) $rose( Sig ) |-> Sig[*(numClk + 1) ] ;
    

In reply to hisingh:
I don’t see the difference.

  • FOR ‘N’ more Clocks: Was ON (@(posedge clk), want ON for N More clocks
  • ON for ‘N’ more Clocks: Was whatever @(posedge clk), want ON for N More clocks