Concerning the "assign" statement

SystemVerilog
1

Hello everyone,

According to the LRM, “assign” is a keyword that is used to do “procedural continuous assignments”, this means assignments inside procedural blocks, which behave like continuous assignments: this means the assignment will happen once the right side element changes.

according to what I understood, “assign” can be used only inside procedural blocks. but I have used it outside any procedural block and it worked, I even had an error if I didn’t use it :


module test(.
            .
            .);

logic[2:0] a;
logic[15:0] b;
//this raises the error:
//  parse error, expecting '(' or IDENTIFIER or INTERFACE_ID near token '='
a = b[14:12];

//this works
assign a = b[14:12];

endmodule

I don’t know why assign worked in a place where it is not supposed to be used, and I don’t know why my first “normal” continuous assignment raised that error.

Thanks in advance.

2

In reply to Yasmine4:

There are different uses of the ‘assign’ statement.

Section 10.3.2 The continuous assignment statement
Section 10.6 Procedural continuous assignments

There are differences based upon where you use them.

Your first “normal” continuous assignment is described in:

Section 10.4.1 Blocking procedural assignments

Read the entire chapter to better understand the different types of assignments.

3

Yes, I happen to have missed seeing the “assign” keyword in the syntax part in 10.3 (continuous assignments)

But why does the blocking continuous assignment raise an error ?

a = b[14:12]
4

In reply to Yasmine4:

There is no such thing a blocking continuous assignment. There are only

  1. procedural blocking assignments
  2. procedural non-blocking assignments
  3. procedural continuous assignments
  4. continuous assignments

Note that you will rarely see (3) used because synthesis tools choose not to support it. They want procedural code to only have on set of sensitivities.

5

In reply to dave_59:

In reply to Yasmine4:
There is no such thing a blocking continuous assignment. There are only

  1. procedural blocking assignments
  2. procedural non-blocking assignments
  3. procedural continuous assignments
  4. continuous assignments

Note that you will rarely see (3) used because synthesis tools choose not to support it. They want procedural code to only have on set of sensitivities.

Yes, my mistake again, I meant to say, why is the normal continuous assignment raising an error that disappears when I use the assign keyword?

6

In reply to Yasmine4:

Because that’s the required syntax for writing a continuous assignment.

7

thank you.