Concatenation issue

SystemVerilog
1

Hi,
I need to calculate a write address as follows:

write_addr = BASE_ADDR + {queue_id, (descr_id + offset1), offset2};

The bit widths and values are as follows:
write_addr[39:0]
BASE_ADDR[31:0] = ‘h1148_0000
queue_id[2:0] = ‘h6
descr_id[7:0]+offset1[9:0] = ‘h1c0
offset2[5:0] = ‘h0

When I print each of the above fields individually, the values are as expected. But when I print the final “write_addr” has the last 12 bits incorrect. I expect 0x71c0 but I see 0x7000.

Anything wrong with concatenation I am doing? I combined “descr_id + offset1” to one variable; I still see the issue.

Appreciate your inputs.

Thanks!

2

In reply to Val.engg:

Hey,

The way concatenation is performed, last 12 bits will be as per your output(12’h7000).

It works like this,


 1148_0000
+0006_7000
 ---------
 114E_7000

Where, value returned by concatenation is 110(queue_id)_01_1100_0000(10’h1c0)_000000(offset2).

Can you explain more about reason behind the concatenation operation!

3

In reply to mayurkubavat:

Thanks mayurkubavat!

My mistake, it IS correct!