Concatenation in `define function in system verilog

Hi all.
I’m trying to use concatenation in `define function but error is coming.
I’m trying to use the concatenated string as module name in module instantiation

The code is


`define mem sram
`define m memory
`define size 1024
`define s size

`define func(mem, s, m) \
    ``mem``_```s // it is giving sram_1024
    ``mem``_```s``_``m  // but it is not giving sram_1024_memory, rather it is giving error

module name;
    `func(`mem, `s, `m) u_mem(); // this module instantiation.
endmodule
module sram_1024_memory;

endmodule

Can anyone please help me out with this to concatenate and acall that module.

Note :
I need to use concatenate 1024 by using “s” only but not using “size”.

Thankyou.

In reply to venkateshla:

There are a couple of typos in the code shown.

In the 4th define, you need to reference size, not size.

There are 3 ``` between _ and s, there should only be 2 ``

There is no need for the 2 at the beginning ofmem

`define mem sram
`define m memory
`define size 1024
`define s `size
 
`define func(mem, s, m) \
    mem``_``s``_``m  // but it is not giving sram_1024_memory, rather it is giving error
 
module name;
    `func(`mem, `s, `m) u_mem(); // this module instantiation.
endmodule
module sram_1024_memory;
  initial $display("%m");
endmodule

In reply to dave_59:

Hi Dave.

Thankyou for you reply.

But

`define mem sram
`define m memory
`define size 1024
`define s `size
 
`define func(mem, s, m) \
    mem``_``s``_``m  // but it is not giving sram_1024_memory, rather it is giving error
 
module name;
    `func(`mem, `s, `m) u_mem(); // this module instantiation.
endmodule
module sram_1024_memory;
  initial $display("%m");
endmodule

But the line
func(mem, s, m) u_mem();
is not instantiating the module sram_1024_memory.
Rather it is throwing error like “`size_memory: not a recognized directive or macro”.

In reply to venkateshla:

Your code works on 3 out of 4 tools on EDAPlayground.

This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.

In reply to dave_59:
Hi Dave,

Are there any other options to do the concatenation and use that concatenated one as module name in module instantiation like above. As this procedure is not working in one of simulator.

In reply to venkateshla:

Use a different simulator or contact your tool vendor directly for support.

In reply to dave_59:

Hi Dave. Is it possible to concatenate a string with parameter. ANd use that concatenated string as module name in instantiation.

`define func(num) \
	NUMBER_``num

module disp#(
	parameter num = 1
)();
	`func(num) u_mem();          // It should call module NUMBER_1();

endmodule

module NUMBER_1();
   initial $dispay("module called");
endmodule


In reply to venkateshla:

No. Macros are simple text replacement before any SystemVerilog code gets parsed. Your macro will produce NUMBER_num.

In reply to dave_59:

`define func(num)
NUMBER_a // or NUMBER_number

module disp#(
parameter num = 1
)
(
input a = num
);
int number = num;
func(a) u_mem(); // It should call module NUMBER_1(); func(number) u_mem();
endmodule

module NUMBER_1();
initial $dispay(“module called”);
endmodule

Then can we concatenate parameter with NUMBER in define with the help of "input a " or "int number" and instantiate module with that. Is it possible to concatenate "input value" or "int value"? If it possible how to do that? If not possible, then is there any other method to concatenate number (which is passed as parameter) with some string in define?