Composition

SystemVerilog
1

Following is an example to understand the difference b/t composition & inheritance


class SomeClass;
      rand bit [3:0] A;
      rand byte B;
 
   constraint c{A<3;}
   
      function void displayItems();
         $display("Class Items: A = %d, B = %d", A, B);
      endfunction
   endclass
 
   class sub;
     rand SomeClass someclass = new(); 
 
     constraint c_C{someclass.B==3;} 
     
      function void display();
         someclass.displayItems();
      endfunction
   endclass
 
module tb();
   sub s_h;
   initial
   begin
      s_h = new();
      s_h.display();
 
      repeat(5)
      begin
         void'(s_h.randomize());
         s_h.display();
        $display("the contents %0d",s_h.someclass.A);
      end
 
      $finish;
   end
endmodule

1]I don’t find much difference here apart from the hierarchical path via the base object to its variable which needs to be specified till the base variable
2]Even the constraints can be applied via object from sub class
I observed that using extends keyword reduces complexity & there is no need of hierarchical access

Question : What are the major difference between Composition & Inheritance ?

Thanks