Hello, Could you please resolve the compiler error that i am getting from my test bench. The code for the module and test bench is as follows:
top module: top_level.
`define window_size 8 //default windows size (measured in strides)
`define stride_length 32//(256 bits)default stride length (measured in bytes)
module top_level(input clk, input reg [7:0] in, output match, output [$clog2(`stride_length*`window_size)+1:0] output_sum, /*output [$clog2(`stride_length):0] out2,*/ input reset, input tick/*output [$clog2(`stride_length):0] out [(`window_size):0] /* input [7:0] feature, mask*/);
// wire [$clog2(`stride_length*`window_size)+1:0] output_sum;
//wire match;
wire [$clog2(`stride_length):0] out [(`window_size):0];
wire [$clog2(`stride_length)-1:0] byteCount1;
wire [$clog2(`stride_length):0] out1;
wire [$clog2(`stride_length):0] out2;
wire [$clog2(`stride_length):0] in1;
//reg [7:0] in;
reg clr;
//reg reset;
//reg tick;
//always @(posedge clk)
//begin
featureMatch matched (match, 8'b11111111, 8'b11111111 , in);
featureCount testCounter (clk, byteCount1, tick, reset);
Counter countup (out2, tick, match, clk);
/*always @(out2)
begin
$display ("out2 ",,out2);
end*/
genreg U (out[`window_size], out2, tick, clk);
windowsum windowsum1 (output_sum, out[`window_size], out2, match, tick, clk, reset);
//end
endmodule
top module test-bench
top_level_tb.sv:
`define window_size 8 //default windows size (measured in strides)
`define stride_length 32 //(256 bits)default stride length (measured in bytes)
module top_level_tb;
// Inputs
reg clk;
reg [7:0] in;
reg [7:0] feature;
reg [7:0] mask;
reg [$clog2(`stride_length * `window_size)+1:0] output_sum;
reg [$clog2(`stride_length):0] out2;
reg [$clog2(`stride_length):0] out [(`window_size):0];
wire match;
reg reset;
// Instantiate the Unit Under Test (UUT)
top_level uut (
.clk(clk),
.in(in),
.match(match),
//.output_sum(output_sum),
//.out2(out2),
.reset(reset),
.tick(tick),
.out(`window_size)(out(`window_size)) // ** Line(25) where error is getting generated ** //
//.feature(feature),
//.mask(mask)
);
initial
begin
// Initialize Inputs
$display("Hello");
clk = 1'b0;
reset = 1'b0;
wait(clk);
reset = 1'b1;
repeat(1000)
begin
in = $random%256;
//feature = $random%256;
//mask = $random%256;
wait(clk);
wait(clk == 0);
$display("match tick outputsum",,match,,tick,,output_sum);
//$display(uut.out2);
end
$finish;
end
always @(clk) begin
#10 clk <= ~clk;
//$display("clk",,clk);
end
endmodule
error: Error: /u0/users/9/rpandit2/DSD2/msim_tut/top_level_tb.sv(25): near “(”: syntax error, unexpected ‘(’, expecting ‘)’