Combining sequence in Assertion

SystemVerilog
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1

Hi All,

I’m looking for some good explanation regarding following operatoins in assertions, preferable with the help of simple example with waveforms


"intersect"
"first_match" 
"throughout" 
"or" 
"within" 
"and"

Please help me out !!
Any kind of SIMPLE and GOOD example for each is really appreciated !!

2

In reply to MLearner:

I’m looking for some good explanation regarding following operatoins in assertions, preferable with the help of simple example with waveforms


"intersect" "first_match" "throughout" "or" "within" "and"

Please help me out !!
Any kind of SIMPLE and GOOD example for each is really appreciated !!

Have you considered a good SystemVerilog Assertions book?
…hint hint …
:)
Below is an example from my SVA Handbook 4th Edition, 2016 ISBN 978-1518681448


An interesting usage of [=] and [->] repetition operators is with the intersect operator, as this gives a bounded range for unbounded non-consecutive repetitions. For example:
a[=2] intersect b[*5] // a must occur twice during window described by b[*5]
a[=2] intersect 1 [*5] // a must occur twice during the next 5 cycles.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi Ben,
I’m glad that you had time to reply my posts, i follow almost all of your posts, would be happy to see you reply on my queries.
Couls you please give me an example if possible with an waveform or anything similar to it, the problem is i have understood its meaning but have confsion in its usage, so if you could help me out with this then it would be great.
And i will surely consider buying your book for SVA.

Have a great day!!
Cheers!

4

In reply to MLearner:
What you are asking is really more of a book, and outside the scope of this forum, which typically provides responses to users being stuck on how to implement an approach, or who are stuck at resolving a particular issue.
There are many presentations and sites that provide information on SVA, a Google search will link you to what you may need.
Again, there are also many books on SVA. Amazon provides free previews of pages of these technical books so that you can see the TOCs and sample pages.
This is really my best recommendations.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
5

In reply to ben@SystemVerilog.us:

Sure Ben, thanks a lot for your time. I will surely have look at you book as well as other material available online.

Good day!