Coding D Flip Flop using Blocking and non blocking assignments and simulation results look same

SystemVerilog
,
1

I am coding D flip Flop using blocking and Non blocking and observing simulation results and I found out that I am getting exact same simulation results .Is this expected.

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DFF using Blocking statements:
module dffb (q, d, clk, rst);
output q;
input d, clk, rst;
reg q;
always @(posedge clk)
if (rst) q = 1’b0;
else q = d;
endmodule

DFF using Non Blocking statements:
module dffb (q, d, clk, rst);
output q;
input d, clk, rst;
reg q;
always @(posedge clk)
if (rst) q <= 1’b0;
else q <= d;
endmodule

Testbench Code
reg CLK, reset, d;
wire q;
parameter PERIOD = 1000;
dffb m1(.q(q),.d(d),.rst(reset),.clk(CLK)); // Instantiate the D_FF
initial CLK <= 0; // Set up clock
always #1 CLK<= ~CLK;
initial begin // Set up signals
d = 0;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1 d =1;
#5 d=0;
#2 d=1;
#1000 $finish;
end
initial begin
// Dump waves
$dumpfile(“dump.vcd”);
$dumpvars(1);
end
endmodule

Waveform :

2

In reply to ritheshraj:

I explained this to you a few days ago.

BTW, the code you entered does not use non-blocking assignments. But assuming that was a typo, in the example here, there is no process reading “q”, so there is no race condition.

However, there is a race condition in the initial block assigments to ‘d’. Sometimes, you change the value of clk at the same time you are changing the value of clk. There is no guarantee if the always block in the D flop module reads the old or new value of d. Using non-blocking assignments to d guarantees it sees the old value.

3

In reply to dave_59:

Hi Dave ,

Can you please give an code example for supporting your statement " if one process writes, and another process reads the same variable synchronized to the same clock edge.".

Thanks,
Rithesh

4

In reply to ritheshraj:

module top;
bit clk;
int A,B;
 always #5 clk = !clk;
 always @(posedge clk) A = A + 1; // process writing to A
 always @(posedge clk) B = A;     // process reading A

endmodule